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Implementation of fast address-space switching and TLB sharing on the StrongARM processor


Adam Wiggins, Harvey Tuch, Volkmar Uhlig and Gernot Heiser

National ICT Australia Ltd.
NSW 2052

School of Computer Science and Engineering
The University of New South Wales
Sydney 2052

University of Karlsruhe


The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires flushing of all CPU caches and the TLB on each context switch, which is very costly. We present an implementation of fast context switches on the architecture in both Linux and the L4 microkernel. It is based on using domain tags as address-space identifiers and delaying cache flushes until a clash of mappings is detected. We observe a reduction of the context-switching overheads by about an order of magnitude compared to the naive scheme presently implemented in Linux.

We also implemented sharing of TLB entries for shared pages, a natural extension of the fast-context-switch approach. Even though the TLBs of the StrongARM are quite small and a potential bottleneck, we found that benefits from sharing TLB entries are generally marginal, and can only be expected to be significant under very restrictive conditions.

BibTeX Entry

    publisher        = {Springer},
    author           = {Adam Wiggins and Harvey Tuch and Volkmar Uhlig and Gernot Heiser},
    month            = {sep},
    year             = {2003},
    title            = {Implementation of Fast Address-Space Switching and {TLB} Sharing on the {StrongARM} Processor},
    booktitle        = {Proceedings of the 8th Asia-Pacific Computer Systems Architecture Conference},
    address          = {Aizu-Wakamatsu City, Japan}