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Itanium — a system implementor's tale

Authors

Charles Gray, Matthew Chapman, Peter Chubb, David Mosberger-Tang and Gernot Heiser

National ICT Australia
Sydney

The University of New South Wales
Sydney 2052
Australia

HP Laboratories
Palo Alto
USA

Abstract

Itanium is a recent, and rather unusual architecture. Its defining feature is that of explicitly-parallel instruction-set computing (EPIC), which moves the onus for exploiting instruction-level parallelism (ILP) from the hardware to the code generator. Itanium theoretically supports high degrees of ILP, but in practice this is hard to achieve, as present compilers are often not up to the task. This is much more a problem for systems than for application code, as compiler writers' efforts tend to be focused on SPEC benchmarks, while the source many performance problems in operating system code only occur during privileged operation. As a result, good OS performance on Itanium is a serious challenge, but the potential rewards are high.

However, EPIC is not the only interesting and novel feature of Itanium. Others include an unusual MMU, a huge register set, and tricky virtualisation issues. We present a number of the challenges posed by the architecture, and show how they can be overcome by clever design and implementation.

BibTeX Entry

  @inproceedings{Gray_CCMH_05,
    author           = {Charles Gray and Matthew Chapman and Peter Chubb and David Mosberger-Tang and Gernot Heiser},
    year             = {2005},
    month            = apr,
    title            = {Itanium --- A System Implementor's Tale},
    booktitle        = {Proceedings of the  2005 USENIX Annual Technical Conference},
    pages            = {264--278},
    address          = {Anaheim, CA, USA}
  }

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